Smallest two-channel low-side gate driver IC

To power the Gpus and cpus used in emerging applications such as artificial intelligence, computer vision, and machine learning, the overall power level of data centers and computing systems is increasing. Therefore, meeting the increasing power density and efficiency requirements requires not only innovation in power switching technologies (such as GaN and SiC) and new topologies, but also further optimization of gate driver ics. Operating frequencies of power semiconductors ranging from hundreds of kHz to MHz, combined with fast switching transients, present new challenges for gate drive circuits that must ensure safe and reliable operation in these critical infrastructure applications. Therefore, the gate driver IC plays a key role in protecting the system and ensuring the robust operation of the system, but also in improving the processing power. To support this, a new generation of dual-channel low-side gate driver ics with 5A source/drain output current capability was recently introduced. Now, the EiceDRIVERTM 2EDN product range has been further expanded with the addition of products in a small lead frame SOT23 (2.9 x 2.8 mm) 6-pin package and an ultra-small leadless TSNP (1.5 x 1.1 mm) 6-pin package. These new package models enable flexible layouts, reduced board space and further optimized gate drive loops to provide better switching performance for high power density applications.
In addition to offering multiple package options, the new EiceDRIVERTM 2EDN product family features an optimized output stage for active clamping of drive voltages, shorter undervoltage lock (UVLO) start times and lower current consumption. Not only that, the high-precision propagation delay allows for two parallel outputs, doubling the current capacity and minimizing dead time losses, resulting in high system efficiency. An example of an application that benefits greatly from achieving two parallel outputs: Synchronous rectifier stages in hybrid switched capacitor converters (HSC) typically operate without gate resistors to achieve the fastest switching transients. Another application example using the EiceDRIVERTM 2EDNxx3x product is the typical center tap rectifier in server SMPS, which performs as well as other products in industry-standard packages (DSO and TSSOP), but takes up a smaller PCB area, which is especially important in space-constrained designs.

Product series overview
The EiceDRIVERTM 2EDNxx3x product family is available in five different packages: DSO (SOIC), TSSOP and WSON in three industrial-grade standard 8-pin packages, as well as SOT23 and TSNP in small 6-pin packages designed for ultra-high power density applications. Each package type offers different peak current capabilities, forward and reverse inputs, and specialized undervoltage locking levels to meet the requirements of different target applications.

The output voltage is actively clamped
During startup, the driver bias voltage on the VDD pin must rise, and if the gate driver IC implements a modulation scheme, then the purpose of the UVLO protection function is to prevent the MOSFET from operating in linear mode. However, in general-purpose gate driver ics, UVLO output clamping is usually achieved using passive clamp resisters (Figure 3, left), so the UVLO activation time is longer, which can result in the output being driven low before it is actively driven, in situations such as when the microcontroller (MCU) and gate driver are powered by different sources. Multiple harmful VGS pulses occur.

In fact, the activation time of resistive passive clamps depends on the RC time constant inside the drive, that is, on the order of a few µs. During this long activation period, the output is usually not properly clamped to a low level, and the MOSFETs may operate in the linear region.

To overcome this problem, the new EiceDRIVERTM 2EDN optimizes the output stage by introducing a fast and reliable output voltage active clamping mechanism, as shown on the right in Figure 3. The active clamping mechanism detects the voltage on the output pin and keeps the VGS in a safe low-voltage state until the UVLO is released. As a result, the driver is able to react faster during the driver VDD voltage start-up process, thereby preventing MOSFET switching action when a low VGS gate voltage is applied to the power switching gate.

Once the driver VDD supply voltage reaches 1.2V, the output voltage active clamping mechanism is activated, and the OUT pin is actively pulled down to the safety shutdown level for approximately 20ns of activation time. The reaction speed is much faster than the RC time constant of the passive clamping mechanism, which can take tens of microseconds or more.

The output waveform of active clamped output voltage is compared with the passive clamped output waveform of similar devices on the market under weak pull-up conditions. The EiceDRIVERTM 2EDNxx3x is more reliable, keeping the OUT voltage at a safe low level during VDD startup.

The output voltage active clamping mechanism also prevents the displacement current flowing through the Miller capacitor Cgd from coupling the voltage to the VGS when the switching node is in a high dV/dt transient, causing the MOSFET to re-turn on. In this case, the output stage of the EiceDRIVERTM 2EDNxx3x detects a fast voltage transient and quickly activates the active clamping mechanism to keep the gate in a safe shutdown state when the VDD falls below the UVLO threshold. Figure 6 compares the two different clamping mechanisms.

Given all of the above considerations, the fast OUTPUT voltage active clamping mechanism can keep the output pin in a safe low-voltage state for a short period of time without exposing the switching gate to unexpected induced noise and potentially harmful linear mode operation.